diff --git a/egs/tedlium2/ASR/conformer_ctc3/.conformer.py.swp b/egs/tedlium2/ASR/conformer_ctc3/.conformer.py.swp
index e643c1b6f..d86db734c 100644
Binary files a/egs/tedlium2/ASR/conformer_ctc3/.conformer.py.swp and b/egs/tedlium2/ASR/conformer_ctc3/.conformer.py.swp differ
diff --git a/egs/tedlium2/ASR/conformer_ctc3/.train.py.swp b/egs/tedlium2/ASR/conformer_ctc3/.train.py.swp
index a7dfe5930..b28d8fb9a 100644
Binary files a/egs/tedlium2/ASR/conformer_ctc3/.train.py.swp and b/egs/tedlium2/ASR/conformer_ctc3/.train.py.swp differ
diff --git a/egs/tedlium2/ASR/conformer_ctc3/conformer.py b/egs/tedlium2/ASR/conformer_ctc3/conformer.py
index 1f8167ace..c05e75d73 100644
--- a/egs/tedlium2/ASR/conformer_ctc3/conformer.py
+++ b/egs/tedlium2/ASR/conformer_ctc3/conformer.py
@@ -455,6 +455,7 @@ class ConformerEncoder(nn.Module):
 
             if i+1 in [3,6,9,12,15] and condition_layer is not None:
                 ctc_out = ctc_output(output, log_prob=False)
+                print(ctc_out)
                 output = output + condition_layer(ctc_out).transpose(0,1)
 
         #output = self.combiner(outputs)